180nm CMOS Op-Amp Design

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I design a 180nm CMOS technology operational amplifier capable of over 80dB of gain and 35MHz of bandwidth. Additionally, ample phase and gain margins ensure closed-loop stability. This project was part of UCSD's ECE 164 class during fall 2022.

The circuit combines a folded cascode and common source amplifier stage to realize high overall gain. Moreover, margin performance was tunable with a compensation resistor and capacitor. Lastly, all MOSFETs were biased with a constant-transconductance reference circuit whose output current was mirrored downstream. Gate voltages were biased with ratiometrically with stacked MOSFET arrangements. Design performance was verified in Cadence Virtuoso.

Six groups were chosen out of roughly 50 to present their designs in front of a panel of Apple engineers. I was awarded the 2nd place prize: an Apple Watch! Though my performance was not the absolute best, the judges saw merit in my design methodology. Thanks, Apple!